Field of the Invention
The present invention relates to a semiconductor device.
Description of the Related Art
The scale of semiconductor integrated circuits is becoming larger. For leading-edge microprocessor units (MPUs), semiconductor chips including more than one billion transistors are being developed. In transistors formed by using a planar process based on the related art, namely, in planar transistors, an n-well region that constitutes a p-channel metal-oxide semiconductor (PMOS) and a p-type silicon substrate (or a p-well region) that constitutes an n-channel metal-oxide semiconductor (NMOS) need to be completely isolated from each other, as described in Hirokazu Yoshizawa, CMOS OP AMP KAIRO JITSUMU SEKKEI NO KISO (CMOS OP Amplifier Circuit, Basics of Practical Design), CQ Publishing Co., Ltd., p. 23. Furthermore, the n-well region and the p-type silicon substrate respectively need body terminals for applying potentials. Accordingly, the planar transistors further need a larger area.
As a solution to address the above-described issue, surrounding gate transistors (SGTs) having a structure, in which the source, the gate, and the drain are arranged in a direction perpendicular to a substrate and the gate surrounds the island-shaped semiconductor layers, has been proposed, and a method for manufacturing SGTs, a CMOS inverter using SGTs, a NAND circuit using SGTs, and a static random access memory (SRAM) cell using SGTs have been disclosed (see Japanese Patent No. 5130596, Japanese Patent No. 5031809, Japanese Patent No. 4756221, and International Publication WO2009/096465, for example).
FIG. 19 is a circuit diagram of a static memory cell (hereinafter referred to as an SRAM cell) using SGTs, and FIG. 20A, FIG. 20B, FIG. 20C, FIG. 20D, and FIG. 21 are layout charts of the SRAM cell or SRAM cells.
The details of the SRAM cell are described in International Publication WO2009/096465, and therefore, a brief description is given below.
FIG. 19 is a circuit diagram of an SRAM cell where Qp1 and Qp2 denote p-channel MOS transistors (hereinafter referred to as PMOS transistors), Qn1, Qn2, Qn3, and Qn4 denote n-channel MOS transistors (hereinafter referred to as NMOS transistors), BL denotes a bit line, BLB denotes an inversion bit line, WL denotes a word line (row line), Vcc denotes a supply voltage, and Vss denotes a reference voltage.
FIG. 20A is a plan view of a layout in which the SRAM cell illustrated in FIG. 19 is formed by using SGTs, for example. FIG. 20B is a cross-sectional view taken along cut line A-A′ in FIG. 20A. FIG. 20C is a cross-sectional view taken along cut line B-B′ in FIG. 20A. FIG. 20D is a cross-sectional view taken along cut line C-C′ in FIG. 20A.
In FIG. 20A, the NMOS transistor Qn2, the PMOS transistor Qp2, and the NMOS transistor Qn4 of the SRAM cell illustrated in FIG. 19 are arranged in the first row (the upper row in FIG. 20A) in order from the left, and the NMOS transistor Qn3, the PMOS transistor Qp1, and the NMOS transistor Qn1 of the SRAM cell illustrated in FIG. 19 are arranged in the second row (the lower row in FIG. 20A) in order from the left.
On an insulating film, such as a buried oxide (BOX) film layer 1, formed on a substrate, planer silicon layers (hereinafter also referred to as lower diffusion layers) 2pa, 2pb, 2na, 2nb, 2nc, and 2nd are formed. The planer silicon layers 2pa and 2pb are respectively formed as p+ diffusion layers, and the planer silicon layers 2na, 2nb, 2nc, and 2nd are respectively formed as n+ diffusion layers, through impurity implantation or the like. Reference numeral 3 denotes a silicide layer formed on the surfaces of the planar silicon layers 2pa, 2pb, 2na, 2nb, 2nc, and 2nd. The silicide layer 3 connects the planer silicon layers 2nc, 2pb, and 2nd to one another, and connects the planer silicon layers 2nb, 2pa, and 2na to one another.
Reference numerals 4n1 and 4n2 denote n-type silicon pillars. Reference numerals 4p1, 4p2, 4p3, and 4p4 denote p-type silicon pillars. Reference numeral 5 denotes a gate insulating film that surrounds the silicon pillars 4n1, 4n2, 4p1, 4p2, 4p3, and 4p4. Reference numeral 6 denotes a gate electrode. Reference numerals 6a, 6b, 6c, and 6d denote gate lines. On the top portions of the silicon pillars 4n1 and 4n2, p+ diffusion layers (hereinafter also referred to as upper diffusion layers) 7p1 and 7p2 are respectively formed through impurity implantation or the like. On the top portions of the silicon pillars 4p1, 4p2, 4p3, and 4p4, n+ diffusion layers (hereinafter also referred to as upper diffusion layers) 7n1, 7n2, 7n3, and 7n4 are respectively formed through impurity implantation or the like. Reference numeral 8 denotes a silicon nitride film for protecting the gate insulating film 5. Reference numerals 9p1, 9p2, 9n1, 9n2, 9n3, and 9n4 denote silicide layers respectively connected to the p+ diffusion layers 7p1 and 7p2 and the n+ diffusion layers 7n1, 7n2, 7n3, and 7n4. Reference numerals 10p1, 10p2, 10n1, 10n2, 10n3, and 10n4 denote contacts that respectively connect the silicide layers 9p1, 9p2, 9n1, 9n2, 9n3, and 9n4 to first metal lines 13c, 13g, 13a, 13f, 13e, and 13h. Reference numeral 11a denotes a contact that connects the gate line 6a to a first metal line 13b. Reference numeral 11b denotes a contact that connects the gate line 6b to a first metal line 13d. Reference numeral 11c denotes a contact that connects the gate line 6c to a first metal line 13i. Reference numeral 11d denotes a contact that connects the gate line 6d to a first metal line 13j. 
Reference numeral 12a denotes a contact that connects the silicide layer 3 connecting the lower diffusion layers 2nb, 2pa, and 2na to one another to the first metal line 13d. Reference numeral 12b denotes a contact that connects the silicide layer 3 connecting the lower diffusion layers 2nd, 2pb, and 2nc to one another to the first metal line 13b. 
The silicon pillar 4n1, the lower diffusion layer 2pa, the upper diffusion layer 7p1, the gate insulating film 5, and the gate electrode 6 constitute the PMOS transistor Qp1. The silicon pillar 4n2, the lower diffusion layer 2pb, the upper diffusion layer 7p2, the gate insulating film 5, and the gate electrode 6 constitute the PMOS transistor Qp2. The silicon pillar 4p1, the lower diffusion layer 2na, the upper diffusion layer 7n1, the gate insulating film 5, and the gate electrode 6 constitute the NMOS transistor Qn1. The silicon pillar 4p2, the lower diffusion layer 2nc, the upper diffusion layer 7n2, the gate insulating film 5, and the gate electrode 6 constitute the NMOS transistor Qn2. The silicon pillar 4p3, the lower diffusion layer 2nb, the upper diffusion layer 7n3, the gate insulating film 5, and the gate electrode 6 constitute the NMOS transistor Qn3. The silicon pillar 4p4, the lower diffusion layer 2nd, the upper diffusion layer 7n4, the gate insulating film 5, and the gate electrode 6 constitute the NMOS transistor Qn4.
To the gate electrodes 6 of the PMOS transistor Qp1 and the NMOS transistor Qn1, the gate line 6a is connected. To the gate electrodes 6 of the PMOS transistor Qp2 and the NMOS transistor Qn2, the gate line 6b is connected. To the gate electrode 6 of the NMOS transistor Qn3, the gate line 6c is connected. To the gate electrode 6 of the NMOS transistor Qn4, the gate line 6d is connected.
The lower diffusion layers 2pa, 2na, and 2nb serve as a common drain of the PMOS transistor Qp1 and the NMOS transistors Qn1 and Qn3 via the silicide layer 3, and are connected to the first metal line 13d via the contact 12a. The first metal line 13d is connected to the gate line 6b via the contact 11b. Similarly, the lower diffusion layers 2pb, 2nc, and 2nd serve as a common drain of the PMOS transistor Qp2 and the NMOS transistors Qn2 and Qn4 via the silicide layer 3, and are connected to the first metal line 13b via the contact 12b. The first metal line 13b is connected to the gate line 6a via the contact 11a. 
The upper diffusion layers 7p1 and 7p2 that respectively serve as the sources of the PMOS transistors Qp1 and Qp2 are respectively connected to the first metal lines 13c and 13g via the silicide layers 9p1 and 9p2 and via the contacts 10p1 and 10p2. The first metal lines 13c and 13g are connected to a second metal line 15a via contacts 14p1 and 14p2 respectively. To the second metal line 15a, the supply voltage Vcc is supplied.
The upper diffusion layers 7n1 and 7n2 that respectively serve as the sources of the NMOS transistors Qn1 and Qn2 are respectively connected to the first metal lines 13a and 13f via the silicide layers 9n1 and 9n2 and via the contacts 10n1 and 10n2. To the first metal lines 13a and 13f, the reference voltage Vss is supplied.
The upper diffusion layer 7n3 that serves as the source of the NMOS transistor Qn3 is connected to the first metal line 13e via the silicide layer 9n3 and via the contact 10n3. The first metal line 13e is connected to a second metal line 15b via a contact 14n3. The second metal line 15b serves as the bit line BL. The upper diffusion layer 7n4 that serves as the source of the NMOS transistor Qn4 is connected to the first metal line 13h via the silicide layer 9n4 and via the contact 10n4. The first metal line 13h is connected to a second metal line 15c via a contact 14n4. The second metal line 15c serves as the inversion bit line BLB. The gate electrodes 6 of the NMOS transistors Qn3 and Qn4 are respectively connected to the gate lines 6c and 6d. The gate line 6d is connected to a third metal line 17 via the contact 11d, the first metal line 13j, a contact 14b, a second metal line 15e, and a contact 16b, as illustrated in FIG. 20D. The third metal line 17 serves as the word line (row selection signal) WL. Similarly, the gate line 6c is connected to the third metal line 17 via the contact 11c, the first metal line 13i, a contact 14a, a second metal line 15d, and a contact 16a. 
Consequently, the SRAM cell illustrated in FIG. 19, which includes the PMOS transistors Qp1 and Qp2 and the NMOS transistors Qn1, Qn2, Qn3, and Qn4 arranged in two rows and three columns as illustrated in FIG. 20A and which has minimum dimensions, can be provided.
Note that a block surrounded by a thin line in FIG. 20A represents the unit of the SRAM cell, and the dimension in the longitudinal direction is denoted by Ly1.
FIG. 21 illustrates an SRAM cell array that includes SRAM cells arranged in a matrix. For convenience sake, four SRAM cells of M(0, 0), M(1, 0), M(0, 1) and M(1, 1) are arranged. As is apparent from FIG. 21, an SRAM cell having a two-row three-column arrangement is assumed to be a minimum unit, and the SRAM cells can be arranged without space therebetween to thereby provide an SRAM cell array with a minimum area.
In an SRAM using SGTs, PMOS transistors and NMOS transistors are completely isolated from each other in the structure, and therefore, well isolation is not needed unlike planar transistors. Further, silicon pillars are floating bodies, and therefore, body terminals for supplying potentials to the wells are not needed unlike planar transistors. Accordingly, the SRAM using SGTs is characterized by a very compact layout (arrangement).
As described above, the most notable feature of SGTs is that a lower layer line that is constituted by a silicide layer located at the lower portion of the silicon pillar closer to the substrate, and an upper layer line that is located at the upper portion of the silicon pillar and is connected to a contact can be used because of the structure of the SGTs.